Conventionally, a PWM system drives a DC motor, for example, producing a drive command signal for a preset PWM cycle, setting the duty ratio of the drive command signal to obtain the torque required for the DC motor, and causing a switching element to perform switching.
In a system block of a DC motor drive apparatus, a CPU for controlling the whole of the DC motor and a PWM control section that receives commands from the CPU via a system bus and produces a drive command signal are provided. The duty ratio of the drive command signal is set to be proportional to the torque required for the DC motor.
Further, Japanese Patent Application Laid Open No. H7-163189, for example, mentions a PWM motor control system using a switching signal that compares a reference signal with a predetermined waveform that is triangular or the like and a command signal for the motor and PWM-modulates the reference signal by means of the command signal.
In addition, Japanese Patent Application Laid Open No. 2000-37079 discloses a PWM circuit comprising a CPU that sets control information and the output of a signal wave constituting a command value based on a signal wave reference signal that is inputted from outside, a PLL circuit to which the signal wave reference signal is inputted that outputs a phase reference signal indicating that a pulse the frequency of which is a fixed multiple of the frequency of the signal wave reference signal and a signal wave reference signal have reached a specified phase, a divider that divides the pulse outputted by the PLL circuit at a division ratio that is preset by the CPU, an up/down counter to which the output of the divider is inputted and which sets a predetermined value that is preset at the timing of the phase reference signal from the PLL circuit, repeats the up and down count between two predetermined values that are set separately from the former predetermined value thus set, and outputs a carrier wave, a comparator that compares the carrier wave and signal wave and, depending on the size of the carrier wave and signal wave, outputs a switching signal that controls the ON/OFF of the switching element of the output converter, the PWM circuit comprising a first register that temporarily holds the division ratio of the divider that is set by the CPU, and a second register to which the temporarily held division ratio is inputted with the timing of the phase reference signal from the PLL circuit and which holds the division ratio and causes the divider to reflect the division ratio. In this PWM circuit, the duty ratio of the drive signal supplied to the load is changed in accordance with the ON/OFF of the switching signal.